Publications

Journals

A. Kokkinis, G. Zervakis, K. Siozios, M. B. Tahoori and J. Henkel, “Enabling Printed Multilayer Perceptrons Realization via Area-Aware Neural Minimization,” IEEE Transactions on Computers, vol. 74, no. 4, pp. 1461-1469, April 2025, doi: 10.1109/TC.2024.3524076.[github]

G. Zervakis, F. Frustaci, O. Spantidi, I. Anagnostopoulos, H. Amrouch and J. Henkel, “Leveraging Highly Approximated Multipliers in DNN Inference,” IEEE Access, doi: 10.1109/ACCESS.2025.3550520.

F. Afentaki, P. C. L. Duarte, G. Zervakis and M. B. Tahoori, “Reducing ADC Front-End Costs During Training of On-Sensor Printed Multilayer Perceptrons,” IEEE Embedded Systems Letters, vol. 16, no. 4, pp. 353-356, Dec. 2024, doi: 10.1109/LES.2024.3447412.[github]

K. Balaskas, A. Karatzas, C. Sad, K. Siozios, I. Anagnostopoulos, G. Zervakis, and J. Henkel, “Hardware-Aware DNN Compression via Diverse Pruning and Mixed-Precision Quantization,” IEEE Trans. Emerg. Top. Comput., pp. 1-1, 2024, doi: 10.1109/TETC.2023.3346944.

G. Armeniakos, G. Zervakis, D. Soudris, M. B. Tahoori, and J. Henkel, “Model-to-Circuit Cross-Approximation For Printed Machine Learning Classifiers,” IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., pp. 1-1, 2023, doi: 10.1109/TCAD.2023.3258668. [github]

G. Armeniakos, G. Zervakis, D. Soudris, and J. Henkel, “Hardware approximate techniques for deep neural network accelerators: A survey,” ACM Comput. Surv., vol. 55, no. 4, pp. 83:1–83:36, 2023, doi: 10.1145/3527156.

G. Armeniakos, G. Zervakis, D. Soudris, M. B. Tahoori, and J. Henkel, “Co-design of approximate multilayer perceptron for ultra-resource constrained printed circuits,” IEEE Trans. Computers, vol. 72, no. 9, pp. 2717–2725, 2023, doi: 10.1109/TC.2023.3251863. [github]

D. Danopoulos, G. Zervakis, K. Siozios, D. Soudris, and J. Henkel, “AdaPT: Fast emulation of approximate DNN accelerators in PyTorch,” IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., vol. 42, no. 6, pp. 2074–2078, 2023, doi: 10.1109/TCAD.2022.3212645. [github]

O. Spantidi, G. Zervakis, S. Alsalamin, I. Roman-Ballesteros, J. Henkel, H. Amrouch, and I. Anagnostopoulos, “Targeting DNN inference via efficient utilization of heterogeneous precision DNN accelerators,” IEEE Trans. Emerg. Top. Comput., vol. 11, no. 1, pp. 112–125, 2023, doi: 10.1109/TETC.2022.3178730.

S. Salamin, G. Zervakis, F. Klemme, H. Kattan, Y. S. Chauhan, J. Henkel, and H. Amrouch, “Impact of NCFET technology on eliminating the cooling cost and boosting the efficiency of google TPU,” IEEE Trans. Computers, vol. 71, no. 4, pp. 906–918, 2022, doi: 10.1109/TC.2021.3065454.

G. Zervakis, I. Anagnostopoulos, S. Salamin, O. Spantidi, I. Roman-Ballesteros, J. Henkel, and H. Amrouch, “Thermal-aware design for approximate DNN accelerators,” IEEE Trans. Computers, vol. 71, no. 10, pp. 2687–2697, 2022, doi: 10.1109/TC.2022.3141054.

O. Spantidi, G. Zervakis, I. Anagnostopoulos, and J. Henkel, “Energy-efficient DNN inference on approximate accelerators through formal property exploration,” IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., vol. 41, no. 11, pp. 3838–3849, 2022, doi: 10.1109/TCAD.2022.3197522.

K. Balaskas, F. Klemme, G. Zervakis, K. Siozios, H. Amrouch, and J. Henkel, “Variability-aware approximate circuit synthesis via genetic optimization,” IEEE Trans. Circuits Syst. I Regul. Pap., vol. 69, no. 10, pp. 4141–4153, 2022, doi: 10.1109/TCSI.2022.3183858.

N. Irtija, I. Anagnostopoulos, G. Zervakis, E.-E. Tsiropoulou, H. Amrouch, and J. Henkel, “Energy efficient edge computing enabled by satisfaction games and approximate computing,” IEEE Trans. Green Commun. Netw., vol. 6, no. 1, pp. 281–294, 2022, doi: 10.1109/TGCN.2021.3122911.

G. Zervakis, I. Anagnostopoulos, S. Salamin, Y. S. Chauhan, J. Henkel, and H. Amrouch, “Impact of NCFET on neural network accelerators,” IEEE Access, vol. 9, pp. 43748–43758, 2021, doi: 10.1109/ACCESS.2021.3066335.

G. Paim, G. Zervakis, G. Pahwa, Y. S. Chauhan, E. A. C. da Costa, S. Bampi, J. Henkel, and H. Amrouch, “On the resiliency of NCFET circuits against voltage over-scaling,” IEEE Trans. Circuits Syst. I Regul. Pap., vol. 68, no. 4, pp. 1481–1492, 2021, doi: 10.1109/TCSI.2021.3058451.

S. Salamin, G. Zervakis, Y. S. Chauhan, J. Henkel, and H. Amrouch, “PROTON: Post-synthesis ferroelectric thickness optimization for NCFET circuits,” IEEE Trans. Circuits Syst. I Regul. Pap., vol. 68, no. 10, pp. 4299–4309, 2021, doi: 10.1109/TCSI.2021.3103860.

K. Balaskas, G. Zervakis, H. Amrouch, J. Henkel, and K. Siozios, “Automated design approximation to overcome circuit aging,” IEEE Trans. Circuits Syst. I Regul. Pap., vol. 68, no. 11, pp. 4710–4721, 2021, doi: 10.1109/TCSI.2021.3106149.

G. Zervakis, H. Amrouch, and J. Henkel, “Design automation of approximate circuits with runtime reconfigurable accuracy,” IEEE Access, vol. 8, pp. 53522–53538, 2020, doi: 10.1109/ACCESS.2020.2981395.

H. Amrouch, G. Zervakis, S. Salamin, H. Kattan, I. Anagnostopoulos, and J. Henkel, “NPU thermal management,” IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., vol. 39, no. 11, pp. 3842–3855, 2020, doi: 10.1109/TCAD.2020.3012753.

Z.-G. Tasoulas, G. Zervakis, I. Anagnostopoulos, H. Amrouch, and J. Henkel, “Weight-oriented approximation for energy-efficient neural network inference accelerators,” IEEE Trans. Circuits Syst., vol. 67–I, no. 12, pp. 4670–4683, 2020, doi: 10.1109/TCSI.2020.3019460.

G. Zervakis, S. Xydis, D. Soudris, and K. Z. Pekmestzi, “Multi-level approximate accelerator synthesis under voltage island constraints,” IEEE Trans. Circuits Syst. II Express Briefs, vol. 66–II, no. 4, pp. 607–611, 2019, doi: 10.1109/TCSII.2018.2869025.

G. Zervakis, K. Koliogeorgi, D. Anagnostos, N. Zompakis, and K. Siozios, “VADER: Voltage-driven netlist pruning for cross-layer approximate arithmetic circuits,” IEEE Trans. Very Large Scale Integr. Syst., vol. 27, no. 6, pp. 1460–1464, 2019, doi: 10.1109/TVLSI.2019.2900160.

V. Leon, G. Zervakis, S. Xydis, D. Soudris, and K. Z. Pekmestzi, “Walking through the energy-error pareto frontier of approximate multipliers,” IEEE Micro, vol. 38, no. 4, pp. 40–49, 2018, doi: 10.1109/MM.2018.043191124.

V. Leon, G. Zervakis, D. Soudris, and K. Z. Pekmestzi, “Approximate hybrid high radix encoding for energy-efficient inexact multipliers,” IEEE Trans. Very Large Scale Integr. Syst., vol. 26, no. 3, pp. 421–430, 2018, doi: 10.1109/TVLSI.2017.2767858.

G. Zervakis, F. Ntouskas, S. Xydis, D. Soudris, and K. Z. Pekmestzi, “VOSsim: A framework for enabling fast voltage overscaling simulation for approximate computing circuits,” IEEE Trans. Very Large Scale Integr. Syst., vol. 26, no. 6, pp. 1204–1208, 2018, doi: 10.1109/TVLSI.2018.2803202.

K. Tsoumanis, N. Axelos, N. Moschopoulos, G. Zervakis, and K. Z. Pekmestzi, “Pre-encoded multipliers based on non-redundant radix-4 signed-digit encoding,” IEEE Trans. Computers, vol. 65, no. 2, pp. 670–676, 2016, doi: 10.1109/TC.2015.2428691.

K. Tsoumanis, S. Xydis, G. Zervakis, and K. Z. Pekmestzi, “Flexible DSP accelerator architecture exploiting carry-save arithmetic,” IEEE Trans. Very Large Scale Integr. Syst., vol. 24, no. 1, pp. 368–372, 2016, doi: 10.1109/TVLSI.2015.2390974.

G. Zervakis, K. Tsoumanis, S. Xydis, D. Soudris, and K. Z. Pekmestzi, “Design-efficient approximate multiplication circuits through partial product perforation,” IEEE Trans. Very Large Scale Integr. Syst., vol. 24, no. 10, pp. 3105–3117, 2016, doi: 10.1109/TVLSI.2016.2535398.

Conferences

G. Saglam, F. Afentaki, G. Zervakis, and M. Tahoori, "Sequential Printed Multilayer Perceptron Circuits for Super-TinyML Multi-Sensory Applications," in Asia and South Pacific Design Automation Conference (ASPDAC '25), Tokyo, Japan, 2025, pp. 30-35, doi: 10.1145/3658617.3697634.

P. C. Lozano Duarte, F. Afentaki, G. Zervakis, and Mehdi Tahoori, "Design and In-training Optimization of Binary Search ADC for Flexible Classifiers," in Asia and South Pacific Design Automation Conference (ASPDAC '25), Tokyo, Japan, 2025, pp. 754 - 760, doi: 10.1145/3658617.3697715.

V. Mrazek, A. Kokkinis, P. Papanikolaou, Z. Vasicek, K. Siozios, G. Tzimpragos, M. Tahoori, and G. Zervakis, "Evolutionary Approximation of Ternary Neurons for On-sensor Printed Neural Networks," in International Conference on Computer Aided Design (ICCAD'24), New Jersey, NY, USA, 2024, pp. 1-6, doi: 10.1145/3676536.3676728. [github]

J. Volk, P. Papanikolaou, G. Zervakis, G. Tzimpragos, "Synthesis of Resource-Efficient Superconducting Circuits with Clock-Free Alternating Logic," in Design Automation Conference (DAC '24), San Fransisco, CA, USA, 2024, pp. 1-6, doi: 10.1145/3649329.3657376.

D. Masouros, A. Ferikoglou, G. Zervakis, S. Xydis, D. Soudris, "Late Breaking Results: Language-level QoR modeling for High-Level Synthesis," in Design Automation Conference (DAC '24), New York, NY, USA, 2024, pp. 1-2, doi: 10.1145/3649329.3663500.

P. Pal, F. Afentaki, H. Zhao, G. Saglam, M. Hefenbrock, G. Zervakis, M. Beigl, M. B. Tahoori, "Fault Sensitivity Analysis of Printed Bespoke Multilayer Perceptron Classifiers," in IEEE European Test Symposium (ETS), The Hague, Netherlands, 2024, pp. 1-6, doi: 10.1109/ETS61313.2024.10567964. [github]

F. Afentaki, M. Hefenbrock, G. Zervakis and M. B. Tahoori, "Embedding Hardware Approximations in Discrete Genetic-Based Training for Printed MLPs," in Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia, Spain, 2024, pp. 1-6, doi: 10.23919/DATE58400.2024.10546879. [github]

G. Armeniakos, P. L. Duarte, P. Pal, G. Zervakis, M. B. Tahoori and D. Soudris, "On-Sensor Printed Machine Learning Classification via Bespoke ADC and Decision Tree Co-Design," in Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia, Spain, 2024, pp. 1-6, doi: 10.23919/DATE58400.2024.10546585. [github]

F. Afentaki, G. Saglam, A. Kokkinis, K. Siozios, G. Zervakis and M. B. Tahoori, "Bespoke Approximation of Multiplication-Accumulation and Activation Targeting Printed Multilayer Perceptrons," in IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Francisco, CA, USA, 2023, pp. 1-9, doi: 10.1109/ICCAD57390.2023.10323613. [github]

A. Kokkinis, G. Zervakis, K. Siozios, M. B. Tahoori, and J. Henkel, “Hardware-aware automated neural minimization for printed multilayer perceptrons,” in Design, automation & test in europe conference & exhibition, DATE 2023, antwerp, belgium, april 17-19, 2023, IEEE, 2023, pp. 1–2. doi: 10.23919/DATE56975.2023.10137161.

J. Henkel, H. Li, A. Raghunathan, M. B. Tahoori, S. Venkataramani, X. Yang, and G. Zervakis, “Approximate computing and the efficient machine learning expedition,” in Proceedings of the 41st IEEE/ACM international conference on computer-aided design, ICCAD 2022, san diego, california, USA, 30 october 2022 - 3 november 2022, pp. 80:1–80:9. doi: 10.1145/3508352.3561105.

G. Armeniakos, G. Zervakis, D. Soudris, M. B. Tahoori, and J. Henkel, “Cross-layer approximation for printed machine learning circuits,” in 2022 design, automation & test in europe conference & exhibition, DATE 2022, antwerp, belgium, march 14-23, 2022, pp. 190–195. doi: 10.23919/DATE54114.2022.9774689. Best paper nomination.
[github]

K. Balaskas, G. Zervakis, K. Siozios, M. B. Tahoori, and J. Henkel, “Approximate decision trees for machine learning classification on tiny printed circuits,” in 23rd international symposium on quality electronic design, ISQED 2022, santa clara, CA, USA, april 6-7, 2022, IEEE, 2022, pp. 1–6. doi: 10.1109/ISQED54688.2022.9806213.

G. Zervakis, H. Saadat, H. Amrouch, A. Gerstlauer, S. Parameswaran, and J. Henkel, “Approximate computing for ML: State-of-the-art, challenges and visions,” in ASPDAC ’21: 26th asia and south pacific design automation conference, tokyo, japan, january 18-21, 2021, ACM, 2021, pp. 189–196. doi: 10.1145/3394885.3431632.

G. Zervakis, O. Spantidi, I. Anagnostopoulos, H. Amrouch, and J. Henkel, “Control variate approximation for DNN accelerators,” in 58th ACM/IEEE design automation conference, DAC 2021, san francisco, CA, USA, december 5-9, 2021, IEEE, 2021, pp. 481–486. doi: 10.1109/DAC18074.2021.9586092.

M. Yayla, K.-H. Chen, G. Zervakis, J. Henkel, J.-J. Chen, and H. Amrouch, “FeFET and NCFET for future neural networks: Visions and opportunities,” in Design, automation & test in europe conference & exhibition, DATE 2021, grenoble, france, february 1-5, 2021, IEEE, 2021, pp. 300–305. doi: 10.23919/DATE51398.2021.9473978.

S. Salamin, G. Zervakis, O. Spantidi, I. Anagnostopoulos, J. Henkel, and H. Amrouch, “Reliability-aware quantization for anti-aging NPUs,” in Design, automation & test in europe conference & exhibition, DATE 2021, grenoble, france, february 1-5, 2021, IEEE, 2021, pp. 1460–1465. doi: 10.23919/DATE51398.2021.9474094.

O. Spantidi, G. Zervakis, I. Anagnostopoulos, H. Amrouch, and J. Henkel, “Positive/negative approximate multipliers for DNN accelerators,” in IEEE/ACM international conference on computer aided design, ICCAD 2021, munich, germany, november 1-4, 2021, IEEE, 2021, pp. 1–9. doi: 10.1109/ICCAD51958.2021.9643491.

N. Zompakis, D. Anagnostos, K. Koliogeorgi, G. Zervakis, and K. Siozios, “A design flow framework for fully-connected neural networks rapid prototyping,” in Proceedings of the international conference on omni-layer intelligent systems, COINS 2019, crete, greece, may 5-7, 2019, pp. 44–49. doi: 10.1145/3312614.3312628.

D. Masouros, K. Koliogeorgi, G. Zervakis, A. Kosvyra, A. Chytas, S. Xydis, I. Chouvarda, and D. Soudris, “Co-design implications of cost-effective on-demand acceleration for cloud healthcare analytics: The AEGLE approach,” in Design, automation & test in europe conference & exhibition, DATE 2019, florence, italy, march 25-29, 2019, J. Teich and F. Fummi, Eds., IEEE, 2019, pp. 622–625. doi: 10.23919/DATE.2019.8714934.

K. Koliogeorgi, G. Zervakis, D. Anagnostos, N. Zompakis, and K. Siozios, “Optimizing SVM classifier through approximate and high level synthesis techniques,” in 8th international conference on modern circuits and systems technologies, MOCAST 2019, thessaloniki, greece, may 13-15, 2019, IEEE, 2019, pp. 1–4. doi: 10.1109/MOCAST.2019.8742064.

K. Koliogeorgi, D. Masouros, G. Zervakis, S. Xydis, T. Becker, G. Gaydadjiev, and D. Soudris, “AEGLE’s cloud infrastructure for resource monitoring and containerized accelerated analytics,” in 2017 IEEE computer society annual symposium on VLSI, ISVLSI 2017, bochum, germany, july 3-5, 2017, pp. 362–367. doi: 10.1109/ISVLSI.2017.70.

G. Zervakis, S. Xydis, and D. Soudris, “Performance-power exploration of software-defined big data analytics: The AEGLE cloud backend,” in International conference on embedded computer systems: Architectures, modeling and simulation, SAMOS 2016, agios konstantinos, samos island, greece, july 17-21, 2016, pp. 312–319. doi: 10.1109/SAMOS.2016.7818364.

G. Zervakis, K. Tsoumanis, S. Xydis, N. Axelos, and K. Z. Pekmestzi, “Approximate multiplier architectures through partial product perforation: Power-area tradeoffs analysis,” in Proceedings of the 25th edition on great lakes symposium on VLSI, GLVLSI 2015, pittsburgh, PA, USA, may 20 - 22, 2015, pp. 229–232. doi: 10.1145/2742060.2742109.

G. Zervakis, S. Xydis, K. Tsoumanis, D. Soudris, and K. Z. Pekmestzi, “Hybrid approximate multiplier architectures for improved power-accuracy trade-offs,” in IEEE/ACM international symposium on low power electronics and design, ISLPED 2015, rome, italy, july 22-24, 2015, IEEE, 2015, pp. 79–84. doi: 10.1109/ISLPED.2015.7273494.

N. Eftaxiopoulos, N. Axelos, G. Zervakis, K. Tsoumanis, and K. Z. Pekmestzi, “Delta DICE: A double node upset resilient latch,” in IEEE 58th international midwest symposium on circuits and systems, MWSCAS 2015, fort collins, CO, USA, august 2-5, 2015, IEEE, 2015, pp. 1–4. doi: 10.1109/MWSCAS.2015.7282145.

G. Zervakis, N. Eftaxiopoulos-Sarris, K. Tsoumanis, N. Axelos, and K. Z. Pekmestzi, “A segmentation-based BISR scheme,” in 19th asia and south pacific design automation conference, ASP-DAC 2014, singapore, january 20-23, 2014, IEEE, 2014, pp. 652–657. doi: 10.1109/ASPDAC.2014.6742965.

N. Eftaxiopoulos-Sarris, G. Zervakis, K. Z. Pekmestzi, and C. Efstathiou, “High performance MAC designs,” in 9th international design and test symposium, IDT 2014, algeries, algeria, december 16-18, 2014, IEEE, 2014, pp. 30–35. doi: 10.1109/IDT.2014.7038582.

N. Eftaxiopoulos-Sarris, N. Axelos, G. Zervakis, K. Tsoumanis, and K. Z. Pekmestzi, “An independent dual gate SOI FinFET soft-error resilient memory cell,” in 9th international design and test symposium, IDT 2014, algeries, algeria, december 16-18, 2014, IEEE, 2014, pp. 39–44. doi: 10.1109/IDT.2014.7038584.

G. Zervakis, N. Eftaxiopoulos-Sarris, K. Tsoumanis, N. Axelos, and K. Z. Pekmestzi, “A high radix montgomery multiplier with concurrent error detection,” in 9th international design and test symposium, IDT 2014, algeries, algeria, december 16-18, 2014, IEEE, 2014, pp. 199–204. doi: 10.1109/IDT.2014.7038613.

N. Axelos, N. Eftaxiopoulos-Sarris, G. Zervakis, K. Tsoumanis, and K. Z. Pekmestzi, “FF-DICE: An 8T soft-error tolerant cell using independent dual gate SOI FinFETs,” in 2014 IEEE 20th international on-line testing symposium, IOLTS 2014, platja d’aro, girona, spain, july 7-9, 2014, IEEE, 2014, pp. 200–201. doi: 10.1109/IOLTS.2014.6873696.

N. Eftaxiopoulos-Sarris, G. Zervakis, K. Tsoumanis, and K. Z. Pekmestzi, “A radiation tolerant and self-repair memory cell,” in 2013 IEEE 19th international on-line testing symposium (IOLTS), chania, crete, greece, july 8-10, 2013, IEEE, 2013, pp. 210–215. doi: 10.1109/IOLTS.2013.6604081.

Books/Book Chapters

G. Zervakis, M. B. Tahoori, and J. Henkel, “Hardware–Software Co-design for Ultra-Resource-Constrained Embedded Machine Learning Inference: A Printed Electronics Use Case,” in Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing, S. Pasricha and M. Shafique, Eds., Springer, Cham., 2024, pp. 201-224. doi: 10.1007/978-3-031-39932-9_8.

G. Zervakis, I. Anagnostopoulos, H. Amrouch, and J. Henkel, “Enabling efficient inference of convolutional neural networks via approximation,” in Approximate computing, W. Liu and F. Lombardi, Eds., Springer International Publishing, 2022, pp. 429–450. doi: 10.1007/978-3-030-98347-5_17.

C. Kachris, E. Koromilas, I. Stamelos, G. Zervakis, S. Xydis, and D. Soudris, “Energy­Efficient Acceleration of Spark Machine Learning Applications on FPGAs,” in Hardware Accelerators in Data Centers, C. Kachris, B. Falsafi, and D. Soudris, Eds., Springer International Publishing, 2019, pp. 87–107. doi: 10.1007/978-3-319-92792-3_5.

G. Zervakis, “On Accelerating Data Analytics: An Introduction to the Approximate Computing Technique,” in Hardware Accelerators in Data Centers, K. Siozios, D. Anagnostos, D. Soudris, and E. Kosmatopoulosm Eds., Springer International Publishing, 2018, pp. 163–180. doi: 10.1007/978-3-030-03640-9_9.